Academic Journal of Engineering and Technology Science, 2025, 8(4); doi: 10.25236/AJETS.2025.080416.
Kong Lingsong1, Lin Pengrong2, Liu Jiansong1
1Beijing Microelectronics Technology Institute, Beijing, China
2Beijing Mxtronics Corporation, Beijing, China
Chiplet package technology brings the advantage of high integration and miniaturization, meanwhile power supply ripple noise of chiplet has become an important index that must be considered in package design. In order to control the low-voltage and high-current power supply ripple noise of a high-performance processor chip, package designer adopts the chip-package power integrity co-analysis method based on Chip Power Model (CPM) to realize the ripple noise and impedance simulation of the chip-package system power network. Based on the co-design, the optimal decoupling capacitor addition strategy is obtained, and the ripple noise of the system power is optimized.
Chip Power Model, Chip-Package Co-Simulation, Power Supply Ripple Noise
Kong Lingsong, Lin Pengrong, Liu Jiansong. Chip-Package Power Integrity Co-Analysis Based on Chip Power Model. Academic Journal of Engineering and Technology Science (2025), Vol. 8, Issue 4: 1-7. https://doi.org/10.25236/AJETS.2025.080416.
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